A configuration of the kind illustrated in FIG. 1 is in use as a data driver for driving the data lines of a liquid crystal display device. Referring to FIG. 1, this conventional data driver includes a shift register 209, data register 208, data latch 207, level shifter 206, grayscale voltage generating circuit 205, decoders 203 and output circuit 202 (amplifiers 201).
The operation of the conventional data driver shown in FIG. 1 will now be described. The shift register 209 outputs shift pulses responsive to a clock signal CLK, and the data register 208 successively up-shifts input video data DATA_IN responsive to the shift pulses from the shift register 209 and delivers the video data in accordance with the number of outputs. The data latch 207 latches the video data delivered by the data register 208 and delivers all of its outputs to the level shifter 206 in unison responsive to the timing of a control signal STB.
The level shifter 206 outputs a signal that is a digital video signal. The digital video signal is converted to an analog grayscale voltage by the circuitry from the decoders 203 to the output circuit 202. The grayscale voltage generating circuit 205 comprises a resistor string including a plurality of resistance elements connected between a power supply VA and a power supply VB, and grayscale voltages the number whereof is equivalent to the number of gray levels are output to the decoders 203 from respective terminals (taps) of the resistor string. Each of the decoders 203 receives each of the grayscale voltages as well as the digital video signal as inputs, selects the grayscale voltage that corresponds to the digital video signal and outputs this grayscale voltage to the output circuit 202. The output circuit 202 amplifies and outputs the grayscale voltages and delivers the amplified voltages to an output terminal group 210. Each output terminal is connected to one end of a data line (not shown) for supplying the grayscale voltage to the pixels of a display device.
The decoders 203 and amplifiers 201, each pair for outputting a grayscale voltage corresponding to the digital video signal, are provided in a number equivalent to the number of outputs. A plurality of decoders 203 commonly receives grayscale voltages output from the grayscale voltage generating circuit 205 through grayscale voltage lines, thereby each grayscale voltage being shared by entire outputs.
In other words, a digital-to-analog converting circuit block is composed by the group of decoders 203, grayscale voltage generating circuit 205 and output circuit 202.
Generally, since the data lines of a liquid crystal display device constitute a large capacitive load, operational amplifiers are used as the amplifiers 201 employed in the output circuit 202. For example, an operational amplifier of the kind shown in FIG. 2, comprises a differential-stage circuit 901 and an output-stage amplifying circuit 903. The differential-stage circuit 901 includes: a differential pair comprising NMOS transistors M3 and M4; a current mirror circuit comprising PMOS transistors M1 and M2; and an NMOS transistor M9 that acts as a constant-current source upon application of a constant bias voltage to its gate terminal. In the example shown in FIG. 2, the output-stage amplifying circuit 903 is constructed as a source-grounded active-load amplifying circuit and comprises a PMOS transistor M7 for receiving and amplifying an output signal from an output point PA of differential-stage circuit 901, and an NMOS transistor M10 that acts as a constant-current source.
Because the node PB and the gate input of the NMOS transistor M3 are connected to form negative feedback, the voltage at the output end (the voltage at an output point PB) stabilizes at a potential at which equilibrium is achieved between the drain current of the PMOS transistor M7 of the output-stage amplifying circuit, which current flows in accordance with the amplified output signal of the differential stage, and the drain current of the NMOS transistor M10 of the constant-current source.
However, a problem which arises with an operational amplifier is the occurrence of output offset that is mainly ascribable to a variation in the characteristics of active elements. The cause of this variation in characteristics is a variation in the oxide film or in the impurity concentration of the MOS transistors, or a variation in element size (W/L, where W and L are channel width and channel length, respectively). These variations in fabrication are decided by the quality of the fabrication process and represent a problem that cannot be avoided.
Generally, offset voltage ascribable to a variation in the transistor characteristics of a differential circuit is proportional to 1/√{square root over ( )} S, where S represents the gate area of the transistor. In order to reduce the offset voltage, therefore, the gate area must be made fairly large. This leads to an increase in chip area. In addition, if the offset voltage itself is large, there is a limit upon the increase in gate area.
In order to solve this problem, use is made of a circuit (an offset-canceling amplifier) for correcting output offset.
A circuit disclosed in Patent Document 1 (Japanese Patent Kokai Publication No. JP-A-11-249624) will be described as a first example of conventional art for correcting output offset. FIG. 3 illustrates the configuration of a high-voltage amplifier circuit (charging amplifier circuit) shown in Patent Document 1, and FIG. 4 illustrates the configuration of a low-voltage amplifier circuit shown in Patent Document 1.
The high-voltage amplifier shown in FIG. 3 includes switching PMOS transistors PB1 and PA1 that connect the gate of an input-stage NMOS (Nch-MOS) transistor NM16 to a (+) or (−) input terminal, and switching PMOS transistors PA2 and PB2 that connect the gate of an input-stage NMOS transistor NM62 to the (+) or (−) input terminal. The high-voltage amplifier further includes switching PMOS transistors PB3 and PA3 that connect the gate electrode of an output-stage PMOS (Pch-MOS) transistor PM56 to the drain of the input-stage NMOS transistor NM61 or NM62. Further, switching PMOS transistors PA4, PB4 are provided for connecting the gates of a PMOS transistor PM53 and PMOS transistor PM54, which form a load circuit, to the drain of the input-stage NMOS transistor MN61 or MN62.
The low-voltage amplifier shown in FIG. 4 has a configuration in which the PMOS and NMOS transistors of the high-voltage amplifier illustrated in FIG. 3 are interchanged. That is, the low-voltage amplifier shown in FIG. 4 includes switching NMOS transistors NB1, NA1 that connect the gate of an input-stage PMOS transistor PM51 to a (+) or (−) input terminal, and switching PMOS transistors NA2 and NB2 that connect the gate of an input-stage PMOS transistor PM52 to the (+) or (−) input terminal. The low-voltage amplifier further includes switching NMOS transistors NB3 and NA3 that connect the gate electrode of an output-stage NMOS transistor NM65 to the drain of the input-stage NMOS transistor PM51 or PM52. Further, switching PMOS transistors NA4 and NB4 are provided for connecting the gates of an NMOS transistor NM63 and NMOS transistor NM64, which form a load circuit, to the drain of the input-stage PMOS transistor PM51 or PM52.
A control signal A is applied to the gates of the switching PMOS transistors PA1 to PA4 and switching NMOS transistors NA1 to NA4, and a control signal B is applied to the gates of the switching PMOS transistors PB1 to PB4 and switching NMOS transistors NB1 to NB4.
The operation of the circuit shown in FIG. 3 will now be described. First, if the control signal A is at the H (high) level and the control signal B is at the L (low) level, the switching PMOS transistors PA1 to PA4 are placed in an OFF (non-conductive) state and the switching PMOS transistors PB1 to PB4 are placed in an ON (conductive) state. Owing to the state of the circuit connections at this time, the gate of the NMOS transistor NM61 is made a non-inverting input, the gate of the NMOS transistor NM62 is made an inverting input, the (+) input terminal is connected to the gate of the NMOS transistor NM61 and the (−) input terminal is connected to the gate of the NMOS transistor NM62.
The output voltage Vout at this time is Vin+Voffh, where Vout is the output voltage, Vin is the input voltage and Voffh is the offset voltage of the high-voltage amplifier. The offset is superimposed on the amplified voltage.
Further, if the control signal A is at the L (low) level and the control signal B is at the H (high) level, the switching PMOS transistors PA1 to PA4 are placed in an ON (conductive) state and the switching PMOS transistors PB1 to PB4 are placed in an OFF (non-conductive) state. Owing to the state of the circuit connections at this time, the gate of the NMOS transistor NM61 is made an inverting input, the gate of the NMOS transistor NM62 is made a non-inverting input, the (−) input terminal is connected to the gate of the NMOS transistor NM61 and the (+) input terminal is connected to the gate of the NMOS transistor NM62.
The output voltage Vout at this time is Vin−Voffh.
Similarly, with regard to operation of the circuit shown in FIG. 4, the polarity of the offset voltage can be made reversible between plus and minus by control whereby the non-inverting input transistor and the inverting input transistor are interchanged by the control signals A and B. That is, if the control signals A and B are at the H and L levels, respectively, the switching NMOS transistors NA1 to NA4 assume an ON state and the switching NMOS transistors NB1 to NB4 assume an OFF state. At this time the gate of the PMOS transistor PM51 is connected to the inverting input (− input terminal) and the gate of the PMOS transistor PM52 to the non-inverting input (+ input terminal). Further, if the control signals A and B are at the L and H levels, respectively, the switching NMOS transistors NA1 to NA4 assume an OFF state and the switching NMOS transistors NB1 to NB4 assume an ON state. At this time the gate of the PMOS transistor PM51 is connected to the non-inverting input (+ input terminal) and the gate of the PMOS transistor PM52 to the inverting input (− input terminal).
The output offset is primarily caused by a variation in characteristics of the differential-pair transistors (NM61, NM62) or (PM51, PM52). The output offset due to the variation in characteristics is unavoidable even if the characteristics of the two transistors constituting the differential pair are designed to be exactly the same. An explanation relating to offset in a differential stage is also set forth in paragraph [0049] of Patent Document 1.
As illustrated above, the amplifier described in Patent Document 1 is such that by reversing the relationship between the H and L levels of the control signals A and B, output offsets that are opposite in sign from each other but equal in absolute value can be produced at the output of the amplifier circuit.
From the standpoint of display quality and prolongation of liquid crystal service life, liquid crystal display devices frequently employ dot inversion drive. When dot inversion drive is used, the positive and negative polarities of applied grayscale voltage become the opposite of each other between mutually adjacent pixels and between mutually adjacent data lines. Accordingly, if a high-voltage amplifier is used to apply a grayscale voltage of positive polarity and a low-voltage amplifier is used to apply a grayscale voltage of negative polarity, two amplifiers are used and are switched between alternatingly frame by frame per pixel. Furthermore, by changing over the relationship between the H level and L level of the control signals A, B every two frames, the output offset is averaged over time in a case where a unit of four frames is observed. As a result, a decline in image quality due to output offset is suppressed.
Although the method of suppressing offset described in Patent Document 1 excels in that no use is made of capacitance, the fact that the absolute value of offset cannot be reduced is a problem. Whereas the video signal changes every data output period and changes every frame unit as well, four frames are required in order to cancel out offset. In the case of a circuit formed by TFTs (thin-film transistors) for which the absolute value of the offset is large, there is a limitation upon the offset suppressing effect afforded by Patent Document 1.
A method of reducing the absolute value of output offset disclosed in Patent Document 2 (Japanese Patent Kokai Publication No. JP-P2005-110065A) will be described as a second example of conventional art. FIG. 5 illustrates a high-voltage amplifier circuit (charging amplifier circuit) shown in Patent Document 2, and FIG. 6 illustrates a switch-control timing chart of the amplifier circuit shown in Patent Document 2.
As illustrated in FIG. 5, the circuit comprises: a differential input section 101 comprising NMOS transistors (input transistors) 111 and 112 whose sources are tied together; a constant-current source 121 connected between the commonly connected sources of the transistors 111 and 112 and a low-potential power source VSS; an active load 102 connected to drains of the NMOS transistors 111 and 112; a switch 10 connecting an input terminal 1 and the gate of the NMOS transistor 111; a capacitance element 5 connected between the gate of NMOS input transistor 112 and a power source V0 (where V0 is an any power source); a driving and output stage 103 connected to an output terminal 2; a switch 11 connecting the output terminal 2 and the gate of the NMOS transistor 112; a switch 13 connecting the output terminal 2 and the gate of the NMOS transistor 111; a switch 12 connecting a drain of the NMOS transistor 111 and the driving and output stage 103; and a switch 14 connecting a drain of the NMOS transistor 112 and the driving and output stage 103.
Next, the operation of the circuit illustrated in FIG. 5 will be described using the switch-control timing chart of FIG. 6. One data output period TDATA is a period in which one signal is output and comprises an offset detection period T01 and an offset-compensated output period T02. The offset detection period T01 is a period for detecting an output voltage that includes offset, and the offset-compensated output period T02 is a period for performing an output operation in which offset has been compensated for based upon a voltage that has been detected and held.
In the offset detection period T01, the switches 10, 11 and 12 are set in an ON state and the switches 13, 14 are set in an OFF state. At this time the gate of the NMOS transistor 111 becomes a non-inverting input and the gate of the NMOS transistor 112 becomes an inverting input. Since the input voltage VIN is amplified and output by voltage-follower operation, the output voltage Vout becomes Vin+Voff (where Voff is the offset voltage). The output potential is held in capacitor 5 at this time.
In the offset-compensated output period T02, the switches 10, 11, 12 are set in an OFF state and the switches 13, 14 are set in an ON state. At this time the gate of the NMOS transistor 111 becomes an inverting input and the gate of the NMOS transistor 112 becomes a non-inverting input. Amplification and output are performed with the potential (Vin+Voff) held in the capacitor 5 serving as the input voltage. In time period T01, the relationship between the polarities of the non-inverting and inverting inputs of the differential pair is the opposite of that in time period T01. Therefore, since the voltage −Voff is output with respect to the input voltage, the output potential Vout at the end of period T02 becomes equal to Vin. As a result, the absolute value of the offset can be corrected to a small value.
A method of reducing the absolute value of output offset disclosed in Patent Document 3 (Japanese Patent Kokai Publication No. JP-P2001-292041A) will be described as a third example of conventional art. FIG. 7 illustrates a high-voltage amplifier circuit (charging amplifier circuit) shown in Patent Document 3, and FIG. 8 illustrates a switch-control timing chart of the amplifier circuit shown in Patent Document 3.
The operation of the offset canceling amplifier set forth in Patent Document 3 will be described with reference to the circuit configuration shown in FIG. 7 and the timing chart depicted in FIG. 8.
In offset detection period T01 constituting one data output period TDATA, switches S1 and S3 are set in an ON state and switch S2 is set in an OFF state. At this time, voltage Vin supplied to input terminal VIN is applied to both transistors of the differential pair (M3, M4). The differential pair (M3, M4) therefore acts as a current source with respect to a current mirror circuit (M1, M2). Further, in the differential pair (MS, M6), the input terminal VIN is connected to the gate of transistor M6 and output terminal VOUT is connected to the gate of transistor MS. The voltage Vout of the output terminal VOUT at this time is stabilized by negative feedback at a voltage (Vin+Voff) that includes offset voltage Voff ascribable to a variation in the characteristics of the transistors in the differential circuit. Since capacitor C1 is connected to the gate of transistor MS, the potential of Vout in the stable state is set in the capacitor C1 at this time.
Next, in offset-compensated output period T02, switches S1 and S3 are set in an OFF state and switch S2 is set in an ON state. The voltage that is applied to the differential pair (M5, M6) at this time remains the same as that in the offset detection period T01. Further, the input terminal VIN remains connected to the gate of transistor M4, and the output terminal VOUT is connected for negative feedback to the gate of transistor M3. As a result, the output voltage Vout stabilizes at a potential that retains the same state as that in the offset detection period T01. That is, in period T02, the output voltage Vout becomes the input voltage Vin and the offset is corrected.
In the first period (offset detection period) according to the method set forth in Patent Document 2, V1 and V1+Voff (=Vout) are applied to the non-inverting input and inverting input. In the second period (offset compensation interval), the relationship between the non-inverting input and inverting input is reversed and V1 (=Vout), V1+Voff1 (=VC1) are applied to the inverting input and non-inverting input. At this time operation is such that the input voltages at the gates of the two transistors of the differential pair and the common source potential are held at the same potentials in the first and second periods, thereby enabling correction of the offset.
Further, in the first period (offset detection period) according to the method set forth in Patent Document 3, Vin+Voff (=Vout) and Vin are applied to the gates of the differential pair (M5, M6), respectively, and Vin is applied in common to the gates of the differential pair (M3, M4). In the second period (offset compensation period), Vin+Voff (=VC1) and Vin are applied to the gates of the transistor pair (M5, M6), respectively, and Vin (=Vout) is applied in common to the gates of the transistor pair (M3, M4). Accordingly, operation is such that the same differential voltage and differential current are held in the first and second periods, and therefore offset can be corrected.
As described above, the methods illustrated in Patent Documents 2 and 3 hold the voltages and currents of the gates of the differential pairs in the first period using a capacitor and change over the connection of the output terminal in the second period, as a result of which operation is such that the voltage input state of the first period is held, thereby making it possible to correct the absolute value of the offset.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-A-11-249624
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2005-110065A
[Patent Document 3] Japanese Patent Kokai Publication No. JP-P2001-292041A